idistributed_compute_technique.h

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/******************************************************************************
 * Copyright 2023 NVIDIA Corporation. All rights reserved.
 *****************************************************************************/
 
#ifndef NVIDIA_INDEX_IDISTRIBUTED_COMPUTE_TECHNIQUE_H
#define NVIDIA_INDEX_IDISTRIBUTED_COMPUTE_TECHNIQUE_H
 
#include <mi/dice.h>
#include <mi/base/interface_declare.h>
 
#include <nv/index/iattribute.h>
#include <nv/index/idistributed_compute_destination_buffer.h>
 
namespace nv {
namespace index {
 
class IDistributed_compute_technique :
    public mi::base::Interface_declare<0xfbde8f4c,0x421e,0x4a6e,0x98,0x68,0x6a,0xe2,0x9b,0xac,0x30,0x4d,
                                       nv::index::IAttribute>
{
public:
    enum Invocation_mode
    {
        INDIVIDUAL,             
        GROUPED_PER_DEVICE,     
        GROUPED_PER_HOST        
    };
 
public:
    virtual void launch_compute(
        IDistributed_compute_destination_buffer_container*  dst_buffer_container,
        mi::neuraylib::IDice_transaction*                   dice_transaction) const = 0;
 
    virtual bool is_gpu_operation() const = 0;
 
    // Returns the expected invocation mode for the compute technique
    virtual Invocation_mode get_invocation_mode() const = 0;
 
    virtual const char* get_configuration() const
    {
        return 0;
    }
};
 
class IDistributed_compute_technique_LOD :
    public mi::base::Interface_declare<0x7c8909d5,0x3cc2,0x415b,0x80,0xef,0x65,0x74,0x99,0x38,0xd6,0xff,
                                       nv::index::IDistributed_compute_technique>
{
};
 
template <mi::Uint32 i_id1, mi::Uint16 i_id2, mi::Uint16 i_id3,
          mi::Uint8  i_id4, mi::Uint8  i_id5, mi::Uint8  i_id6,  mi::Uint8 i_id7,
          mi::Uint8  i_id8, mi::Uint8  i_id9, mi::Uint8  i_id10, mi::Uint8 i_id11,
          class I = nv::index::IDistributed_compute_technique>
class Distributed_compute_technique :
    public mi::neuraylib::Element<i_id1,i_id2,i_id3,i_id4,i_id5,i_id6,i_id7,i_id8,i_id9,i_id10,i_id11,I>
{
public:
    virtual mi::base::Uuid get_attribute_class() const
    {
        return nv::index::IDistributed_compute_technique::IID();
    }
 
    virtual bool multiple_active_instances() const
    {
        return false;
    }
 
    virtual void set_enabled(bool enable)
    {
        // avoid warnings
        (void) enable;
    }
 
    virtual bool get_enabled() const
    {
        return true;
    }
 
    virtual void set_meta_data(mi::neuraylib::Tag_struct tag)
    {
      (void) tag;
    }
 
    virtual mi::neuraylib::Tag_struct get_meta_data() const { return mi::neuraylib::NULL_TAG; }
 
    virtual bool is_gpu_operation() const
    {
        return false;
    }
 
    // Per default we want individual invocations
    virtual IDistributed_compute_technique::Invocation_mode get_invocation_mode() const
    {
        return IDistributed_compute_technique::INDIVIDUAL;
    }
 
    // Keep compatibility with the old launch_compute() interface
    virtual void launch_compute(
        mi::neuraylib::IDice_transaction*         dice_transaction,
        IDistributed_compute_destination_buffer*  dst_buffer) const
    {
        (void) dice_transaction;
        (void) dst_buffer;
    }
 
    virtual void launch_compute(
        IDistributed_compute_destination_buffer_container*  dst_buffer_container,
        mi::neuraylib::IDice_transaction*                   dice_transaction) const
    {
        if (dst_buffer_container && dst_buffer_container->get_nb_destination_buffers() > 0u) {
            return launch_compute(dice_transaction, dst_buffer_container->get_destination_buffer(0u));
        }
    }
};
 
 
template <mi::Uint32 i_id1, mi::Uint16 i_id2, mi::Uint16 i_id3,
          mi::Uint8  i_id4, mi::Uint8  i_id5, mi::Uint8  i_id6,  mi::Uint8 i_id7,
          mi::Uint8  i_id8, mi::Uint8  i_id9, mi::Uint8  i_id10, mi::Uint8 i_id11,
          class I = nv::index::IDistributed_compute_technique_LOD>
class Distributed_compute_technique_LOD :
    public nv::index::Distributed_compute_technique<i_id1,i_id2,i_id3,i_id4,i_id5,i_id6,i_id7,i_id8,i_id9,i_id10,i_id11,I>
{
};
 
} // namespace index
} // namespace nv
 
#endif // NVIDIA_INDEX_IDISTRIBUTED_COMPUTE_TECHNIQUE_H