irendering_kernel_programs.h

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/******************************************************************************
 * Copyright 2023 NVIDIA Corporation. All rights reserved.
 *****************************************************************************/
 
#ifndef NVIDIA_INDEX_IRENDERING_KERNEL_PROGRAMS_H
#define NVIDIA_INDEX_IRENDERING_KERNEL_PROGRAMS_H
 
#include <mi/dice.h>
 
#include <nv/index/iattribute.h>
 
namespace nv {
namespace index {
 
class IRendering_kernel_program :
    public mi::base::Interface_declare<0x4953ee6c,0x1099,0x47de,0x94,0xa8,0x5e,0xb7,0x17,0xe4,0x83,0x7d,
                                       nv::index::IAttribute>
{
public:
    struct Program_options
    {
        mi::Sint32                                  max_registers;  
        mi::math::Vector_struct<mi::Uint32, 2>      block_size;     
        mi::Uint32                                  debug_flags;    
    };
 
public:
    virtual void set_program_source(const char* prog_src) = 0;
 
    virtual const char* get_program_source() const = 0;
 
    virtual void set_program_options(const Program_options& prog_options) = 0;
 
    virtual const Program_options& get_program_options() const = 0;
};
 
class IRendering_kernel_program_headers :
    public mi::base::Interface_declare<0xa5edda1a,0x9a97,0x40c1,0xa2,0xe7,0xf2,0x44,0x2d,0x2d,0x55,0xc7,
                                       nv::index::IAttribute>
{
public:
    virtual void set_header(
        const char* include_name,
        const char* header_source) = 0;
 
    virtual const char* get_header(const char* include_name) const = 0;
 
    virtual mi::Uint32 get_nb_headers() const = 0;
 
    virtual void get_header(
        mi::Uint32   index,
        const char** include_name_out,
        const char** header_source_out) const = 0;
 
    virtual void clear() = 0;
};
 
class IRendering_kernel_program_parameters :
    public mi::base::Interface_declare<0x82ad1cdf,0xcbac,0x452f,0x9b,0x63,0x13,0xe4,0x94,0xc9,0xbf,0xaa,
                                       nv::index::IAttribute>
{
public:
    virtual mi::Uint32 get_nb_buffer_slots() const = 0;
 
    virtual mi::Size get_max_buffer_size() const = 0;
 
    virtual mi::Size get_array_offset_alignment() const = 0;
 
    virtual bool set_buffer_data(
        mi::Uint32       slot_idx,
        const void*      data,
        mi::Size         data_size) = 0;
};
 
class IRendering_kernel_program_scene_element_mapping :
    public mi::base::Interface_declare<0x8ecf51a1,0xdf74,0x47a1,0x84,0x27,0xae,0xb0,0x14,0xee,0x52,0xc8,
                                       nv::index::IAttribute>
{
public:
    virtual mi::Uint32 get_nb_slots() const = 0;
 
    virtual bool set_mapping(
        mi::Uint32                 slot_idx,
        mi::neuraylib::Tag_struct  data_tag) = 0;
 
    enum Query_reference
    {
        RELATIVE_QUERY_BOUNDING_BOX = 0, 
        ABSOLUTE_QUERY_BOUNDING_BOX = 1  
    };
 
    virtual bool set_mapping(
        mi::Uint32                                   slot_idx,
        mi::neuraylib::Tag_struct                    data_tag,
        const mi::math::Bbox_struct<mi::Float32, 3>& query_bbox,
        Query_reference                              reference = RELATIVE_QUERY_BOUNDING_BOX) = 0;
 
    virtual mi::neuraylib::Tag_struct get_mapping(
        mi::Uint32                 slot_idx) const = 0;
};
 
class IVolume_sample_program :
    public mi::base::Interface_declare<0x4c2b9169,0xb377,0x452a,0x8f,0xfa,0x87,0x70,0x35,0xd9,0xa2,0xe8,
                                       nv::index::IRendering_kernel_program>
{
};
 
class ISurface_sample_program :
    public mi::base::Interface_declare<0x861e254b,0x6ade,0x4579,0x93,0x15,0x23,0x2d,0x5c,0x3f,0xe5,0xfd,
                                       nv::index::IRendering_kernel_program>
{
};
 
} // namespace index
} // namespace nv
 
#endif // NVIDIA_INDEX_IRENDERING_KERNEL_PROGRAMS_H