ischeduling_configuration.h

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/***************************************************************************************************
 * Copyright 2023 NVIDIA Corporation. All rights reserved.
 **************************************************************************************************/
 
#ifndef MI_NEURAYLIB_ISCHEDULING_CONFIGURATION_H
#define MI_NEURAYLIB_ISCHEDULING_CONFIGURATION_H
 
#include <mi/base/interface_declare.h>
 
namespace mi {
 
namespace neuraylib {
 
class IScheduling_configuration : public
    mi::base::Interface_declare<0x4f1fe336,0x111a,0x44c3,0xb2,0x95,0xa3,0x30,0xf0,0xb6,0xc2,0x05>
{
public:
    virtual Sint32 set_cpu_load_limit( Float32 limit) = 0;
 
    virtual Float32 get_cpu_load_limit() const = 0;
 
    virtual Sint32 set_gpu_load_limit( Float32 limit) = 0;
 
    virtual Float32 get_gpu_load_limit() const = 0;
 
    virtual Sint32 set_accept_delegations( bool value) = 0;
 
    virtual bool get_accept_delegations() const = 0;
 
    virtual Sint32 set_work_delegation_enabled( bool value) = 0;
 
    virtual bool get_work_delegation_enabled() const = 0;
 
    virtual Sint32 set_gpu_work_delegation_enabled( bool value) = 0;
 
    virtual bool get_gpu_work_delegation_enabled() const = 0;
 
    virtual Sint32 set_thread_affinity_enabled( bool value) = 0;
 
    virtual bool get_thread_affinity_enabled() const = 0;
};
 // end group mi_neuray_configuration
 
} // namespace neuraylib
 
} // namespace mi
 
#endif // MI_NEURAYLIB_ISCHEDULING_CONFIGURATION_H