irdma_context.h

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/***************************************************************************************************
 * Copyright 2023 NVIDIA Corporation. All rights reserved.
 **************************************************************************************************/
 
#ifndef MI_NEURAYLIB_IRDMA_CONTEXT_H
#define MI_NEURAYLIB_IRDMA_CONTEXT_H
 
#include <mi/base/interface_declare.h>
 
namespace mi {
 
namespace neuraylib {
 
class IRDMA_buffer : public
    mi::base::Interface_declare<0x9b7b00e6,0x9539,0x4a07,0x88,0x1a,0x9d,0xdd,0x91,0x5c,0x6d,0xfe>
{
public:
    virtual Uint64 get_id() const = 0;
 
    virtual Sint32 get_gpu_id() const = 0;
 
    virtual const Uint8* get_data() const = 0;
 
    virtual Uint8* get_data() = 0;
 
    virtual Size get_size() const = 0;
 
    virtual const IRDMA_buffer* duplicate( Size offset, Size size) const = 0;
 
    virtual IRDMA_buffer* duplicate( Size offset, Size size) = 0;
 
    virtual bool is_gpudirect() = 0;
};
 
class IRDMA_context : public
    mi::base::Interface_declare<0x5f3980e9,0xfadc,0x478d,0xbb,0x18,0x44,0x10,0xa4,0x6f,0xf7,0xb5>
{
public:
    virtual IRDMA_buffer* get_write_memory( Size size, Sint32 gpu_id = -1) = 0;
 
    virtual IRDMA_buffer* get_read_memory( Size size, Sint32 gpu_id = -1) = 0;
 
    virtual IRDMA_buffer* wrap_user_buffer(
        Uint8* data, Size size, Sint32 gpu_id = -1) = 0;
 
    virtual Sint32 flush( IRDMA_buffer* buffer) = 0;
};
 // end group mi_neuray_dice
 
} // namespace neuraylib
 
} // namespace mi
 
#endif // MI_NEURAYLIB_IRDMA_CONTEXT_H